CHAPTER ONE

1.0 INTRODUCTION

In a synchronous system, operations are coordinated under the centralized control of a fixed-rate clock signal or several clocks. An asynchronous digital system, in contrast, has no global clock: instead, it operates under distributed control, with concurrent hardware components communicating and synchronizing on channels. Asynchronous communication is typically performed on channels. Communication is used both to synchronize operations of the concurrent system as well as to pass data. A simple channel typically consists of two wires: a request and an acknowledge. In a ‘4-phase handshaking protocol’ (or return-to-zero), the request is asserted by the sender component, and the receiver responds by asserting the acknowledge; then both signals are deasserted in turn. In a ‘2-phase handshaking protocol’ (or transition-signalling), the requester simply toggles the value on the request wire (once), and the receiver responds by toggling the value on the acknowledge wire. Channels can also be extended to communicate data Asynchronous datapaths are typically encoded using several schemes. Robust schemes use two wires or ‘rails’ for each bit, called ‘dual-rail encoding’. In this case, first rail is asserted to transmit a 0 value, or the second rail is asserted to transmit a 1 value. The asserted rail is then reset to zero before the next data value is transmitted, thereby indicating ‘no data’ or a ‘spacer’ state. A less robust, but widely-used and practical scheme, is called ‘single-rail bundled data’. Here, a single-rail (i.e. synchronous-style) function block can be used, with an accompanying worst-case matched delay. After valid data inputs arrive, a request signal is asserted as the input to the matched delay. When the matched delay produces a ‘done’ output, the block guaranteed to have completed computation. While this scheme has timing constraints, they are simple, localized (unlike in synchronous systems), and one-sided, hence are usually easy to validate.

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